1. Field of the Invention
The present invention relates to a low power consumption and high speed sense amplifier, an SRAM using such a sense amplifier, and a microprocessor assembled with such an SRAM.
2. Description of the Related Art
In an SRAM, a plurality of memory cells are connected to a plurality of bit lines (BL, /BL). Each memory cell is connected to one of a plurality of word lines (WL) disposed in the direction perpendicular to the bit lines. One word line selected by a decoder is set to a high level, and the other word lines are set to a low level. A selected memory cell outputs a voltage signal equal to a power supply voltage, to one of its bit lines BL and /BL and a voltage signal slightly lower than the power supply voltage to the other bit line, in accordance with the binary information stored in the selected memory cell. The data ("1" or "0") stored in the memory cell selected by the decoder circuit appears as having an extremely small voltage difference between the pair of bit lines connected to the cell. This voltage difference is generally in the range of several tens mV to one hundred mV. If the data of a memory cell is "1", the potential at BL is higher than /BL, and if the data is "0", the potential at BL is lower than /BL. A sense amplifier differentially amplifies this small voltage.
FIGS. 2, 3, 4A are circuit diagrams of conventional sense amplifiers for SRAMs.
The sense amplifier shown in FIG. 2 is called a latch type sense amplifier which is described, for example, in an article entitled "A 9-ns 1-Mbit CMOS SRAM", by K. Sasaki et al, IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989, pp. 1219-1224.
Referring to FIG. 2, a small potential difference between a pair of bit lines BL and /BL is supplied to n-type MOS transistors MN4 and MN5 and outputted from an output node pair OUT and /OUT. Assuming that the level of BL is high, and the level of /BL is low, MN4 eventually turns on and MN5 turns off. Therefore, a high level voltage appears at the output node on the Vcc side of MN5, and a low level voltage appears at the output node on the Vcc side of MN4. This voltage difference is positively fed back by two p-type MOS transistors MP5 and MP6 constituting a latch, and outputted as complementary signals to the output ports OUT and /OUT. While the sense amplifier outputs the complementary signals, a voltage equal to the power supply voltage Vcc is applied to the gate SAC of a transistor MN6 to maintain it on.
The sense amplifier shown in FIG. 3 is called a current Miller type sense amplifier which is described, for example, in an article entitled "A 256K CMOS SRAM with Variable-Impedance Loads", by S. Yamamoto, et al., ISSCC Digest of Technical Papers, February 1985, pp. 58-59.
Referring to FIG. 3, a small potential difference between a pair of bit lines BL and /BL is amplified by the sense amplifier in the same manner described with FIG. 2, and complementary signals are outputted to the output node pair OUT and /OUT. If the level of BL is high and that of /BL is low, MN7 is eventually turned on and MN 10 is turned off. Therefore, a high level voltage appears at the output node on the Vcc side of MN10, and a low level voltage appears at the output node on the Vcc side of MN7. Then, transistors MN8, MP8, and MP7 turn off, and transistors MN9, MP9, and MP10 turn on, by the Miller effect, and the amplified complementary signals are outputted to the output ports OUT and /OUT. A transistor MN11 provides the same function as MN6 shown in FIG. 2.
The sense amplifier shown in FIG. 4A is described, for example, in an article entitled "A 1-V Operating 256-kb Full-cmos sram", by A. Sekiyama, et al., IEEE Journal of Solid-State Circuits, Vol. 27, No. 5, May 1992, pp. 776-782.
FIG. 4A is a circuit diagram of the sense amplifier, and FIG. 4B is a timing chart showing a change of signals with time.
When sense amplifier active signals .PHI.SA and /.PHI.SA become high and low, respectively (refer to voltage waveforms shown in FIG. 4B), both transistors MN14 and MP13 turn on so that a latch circuit constituted by transistors MP11, MP12, MN12, and MN13 is made active. A potential difference between bit lines BL and /BL is therefore amplified and outputted to the bit lines BL and /bl. A small potential difference between the bit lines BL and /BL as shown in FIG. 4B eventually turns out to be a GND level voltage on the BL side node of MN13 and a Vcc level voltage on the BL side of MN12 because MN13 and MP11 turn on eventually and MP12 and MN12 turn off eventually. The GND level voltage and Vcc level voltage therefore appear on the bit lines BL and /BL.
In order to speed up the operation of a sense amplifier for SRAMs, plural stage arrangements of sense amplifiers have been used. For example, as shown in FIG. 9, a two stage configuration including local sense amplifiers and a main sense amplifier has been commonly used. As shown in FIG. 9, when a memory cell is selected by a decoder, signals amplified by a local sense amplifier corresponding to the selected block are transferred via a block selector controlled by the decoder circuit to data buses (DB, /DB). The signals on the data buses are then amplified by the main sense amplifier. Such a two stage configuration is described, for example, in an article entitled "A 4-Mb CMOS SRAM with a PMOS Thin-Film-Transistor Load Cell", by T. Ootani et al., IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990, pp. 1082-1092.
Conventional sense amplifiers, however, have a trade-off between low power consumption and high speed operation. Specifically, the latch type sense amplifier shown in FIG. 2 and the current Miller type sense amplifier shown in FIG. 3 have a large power consumption although they operate at a high speed, whereas the sense amplifier shown in FIG. 4 operates at a low speed although it has a small power consumption.
More specifically, in the sense amplifiers shown in FIGS. 2 and 3, a d.c. current continuously flows while the complementary signals (OUT, /OUT) are outputted, increasing the power consumption. Namely, since the potentials of the bit lines BL and /BL are generally the same during the initial stage, the transistors MN4 and MN5 of the sense amplifier shown in FIG. 2 both turn on, and one of the output node pair OUT and /OUT at a low level thereby turning on one of MP5 and MP6. During the active operation of the sense amplifier, MN6 remains turned on. As a result, a d.c. current always flows either through a current path A or B.
Also in the sense amplifier shown in FIG. 3, because generally have the same potential BL and /BL generally have the same potential during the initial stage, MN7 and MN10 both turn on, and one of the output node pair OUT and /OUT is at a high level thereby turning on MP10 or MP7. During the active operation of the sense amplifier, MN11 remains turned on. As a result, a d.c. current always flows either through a current path C or D.
In the sense amplifier shown in FIG. 4, a d.c. current will not flow after the output levels have been established, resulting in a relatively small power consumption. Namely, when the bit line BL takes a high level (Vcc) and the bit line /BL takes a low level (GND), both MP12 and MN12 turn off and no d.c. current flows. However, during the active operation of the sense amplifier, it is required to drive the bit lines BL and /BL, lowering the sense operation speed. An extremely large number of memory cells are usually connected to the bit lines BL and /BL (refer to FIG. 5A). It is therefore necessary for the sense amplifier to drive a large load (parasitic capacitances of memory cells indicated as C1 and C2 in FIG. 4A).
As described above, the sense amplifiers shown in FIGS. 2 and 3 have a large power consumption, and the sense amplifier shown in FIG. 4A has a relatively slow operation speed. It is difficult for conventional sense amplifiers to obtain both the low power consumption and high speed operation. In the case of a two-stage configuration sense system having a main sense amplifier and local sense amplifiers shown in FIG. 9, data buses DB and /DB are required to be extended in the direction of disposing blocks 1 to N by a considerably long distance, increasing the wiring capacitance. Therefore, a large current I1 will flow when charging/discharging the data busses, resulting in a large power consumption. As a means for reducing the charge/discharge current I1, it is possible for the block selector to be provided with a circuit for reducing a voltage swing on the data buses. The voltage swing reduction by such a circuit uses a voltage V.sub.bias shown in FIG. 10A or a MOS threshold value shown in FIG. 10B. In this case, however, if the sense amplifier shown in FIG. 2 or 3 is used as the main sense amplifier, a d.c. current I2 will flow through the main sense amplifier because, as described previously, a d.c. current will flow if complementary signals having a small potential difference are supplied. As a result, even if the voltage swing reduction on the data buses is effected to reduce the charge/discharge current I1, the d.c. current I2 of the main sense amplifier increases. The total power consumption of the two-stage sense amplifier cannot, therefore, effectively be reduced.
It is essential to allow the voltages on the data buses DB and /DB to swing fully when the outputs have been established. Therefore, even if the sense amplifier shown in FIG. 4 is used as the main sense amplifier, it is principally impossible to incorporate such a means for reducing a voltage swing on the data buses.
As described so far, even if the voltage swing on the data buses DB and /DB is reduced at the local sense amplifier, the power consumption cannot effectively be reduced if the conventional sense amplifier shown in FIGS. 2 and 3 is used as the main sense amplifier. If the sense amplifier shown in FIG. 4A is used as the main sense amplifier, it is principally impossible to reduce the voltage swing on the data buses.